128) In a digital counter circuit feedback loop is introduced to

Improve distortion

Improve stability

Reduce the number of input pulses to reset the counter

Asynchronous input and output pulses

Answer is:

Reduce the number of input pulses to reset the counter

Digital Logic MCQ with Answers

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129) Which of the following conditions must be met to avoid race around problem ?

Δ t < t_p < T

T > Δt > t_p

2 t_p < Δt < T

None of these

Answer is:

T > Δt > t_p

130) Match List I with List II and select the correct answer form the codes given below the list
List I
A. A shift register can be
B. A multiplexer
C. A decoder can
List II
1.for parallel to serial conversion
2.to generate memory can be used chip select
3.for parallel to serial conversion

3 1 2

2 3 1

1 3 2

1 2 3

Answer is:

1 3 2

131) With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip-flops required ?

Answer is:

6

132) A pulse train can be delayed by a finite number of clock periods using

A serial-in serial-out shift register

A serial-in parallel-out shift register

Both (a) and (b)

A parallel-in parallel-out shift register

Answer is:

A parallel-in parallel-out shift register

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128) In a digital counter circuit feedback loop is introduced to

Reduce the number of input pulses to reset the counter

Digital Logic MCQ with Answers

Related Digital Logic MCQ with Answers

129) Which of the following conditions must be met to avoid race around problem ?

T > Δt > tp

130) Match List I with List II and select the correct answer form the codes given below the list List I A. A shift register can be B. A multiplexer C. A decoder can List II 1.for parallel to serial conversion 2.to generate memory can be used chip select 3.for parallel to serial conversion

1 3 2

131) With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip-flops required ?

6

132) A pulse train can be delayed by a finite number of clock periods using

A parallel-in parallel-out shift register

Digital Logic MCQ with Answers

T > Δt > t_p

130) Match List I with List II and select the correct answer form the codes given below the list
List I
A. A shift register can be
B. A multiplexer
C. A decoder can
List II
1.for parallel to serial conversion
2.to generate memory can be used chip select
3.for parallel to serial conversion