1011.1011

1101.111

1000.111

all of these

81

72

71

all of these

is flagged whenever there is carry from sign bit addition

cannot occur when a positive value is added to a negative value

is flagged when the carries from sign bit and previous bit match

none of these

Improve distortion

Improve stability

Reduce the number of input pulses to reset the counter

Asynchronous input and output pulses

Δ t < t_p < T

T > Δt > t_p

2 t_p < Δt < T

None of these