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Computer Science Set-1
Digital Logic
149

Digital Logic MCQ with Answers

149) In a positive edge triggered JK flip-flop, a low J and low K produces

No change

Low state

High state

None of these

Answer is:

No change

Digital Logic MCQ with Answers

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Related Digital Logic MCQ with Answers

150) When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is

JK flip-flop

D flip-flop

SR flip-flop

Master slave JK flip-flop

Answer is:

D flip-flop

151) A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the ′toggle ′ mode. The frequency of the signal at the output will be

1 MHz

2 MHz

6 MHz

8 MHz

Answer is:

8 MHz

152) The master slave JK lip-flop is effectively a combination of

A SR flip-flop and a T flip-flop

An SR flip-lfop and a D flip-flop

A T flip-flop and a D flip-flop

Two D flip-flops

Answer is:

A SR flip-flop and a T flip-flop

153) It is difficult to design asynchronous sequential circuit because

External clock is to be provided

It is more complex

Both (a) and (b)

Generally they involve stability problem

Answer is:

Generally they involve stability problem

Digital Logic MCQ with Answers

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